Search - pipeline verilog

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[Embeded-SCM Develop] cf_fp_mul_p_5_10 DL : 0: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Date : 2008-10-13 Size : 4.66kb User : 丁谨
[Embeded-SCM Develop] cf_fp_mul_p_8_23 DL : 0: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Date : 2008-10-13 Size : 6.35kb User : 丁谨
[Embeded-SCM Develop] cf_fp_mul_p_5_10 DL : 0: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Date : 2025-07-16 Size : 4kb User : 丁谨
[Embeded-SCM Develop] cf_fp_mul_p_8_23 DL : 0: verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
Date : 2025-07-16 Size : 6kb User : 丁谨
[VHDL-FPGA-Verilog] pipe DL : 0: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Date : 2025-07-16 Size : 5kb User : 刘陆陆
[VHDL-FPGA-Verilog] alu DL : 0: verilog编写的alu模块-Verilog modules prepared by the ALU
Date : 2025-07-16 Size : 1kb User : 刘陆陆
[Other] statemachine11.2 DL : 0: 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
Date : 2025-07-16 Size : 2kb User : 陶玉辉
[VHDL-FPGA-Verilog] riscmcu DL : 0: 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
Date : 2025-07-16 Size : 78kb User : 磊
[VHDL-FPGA-Verilog] add DL : 0: 流水线乘法器与加法器开发环境：Modelsim（verilog hdl）-Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
Date : 2025-07-16 Size : 1kb User : 来法旧佛
[ARM-PowerPC-ColdFire-MIPS] MIPS DL : 1: 带分支预测的MIPS流水线的verilog原代码。详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Date : 2025-07-16 Size : 17kb User : 张鹤
[Windows Develop] CPU_verilog DL : 0: 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
Date : 2025-07-16 Size : 62kb User : xq
[VHDL-FPGA-Verilog] cordic DL : 0: vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
Date : 2025-07-16 Size : 1kb User : lmy
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Date : 2025-07-16 Size : 4.72mb User : 石
[VHDL-FPGA-Verilog] PipelineCPU DL : 0: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Date : 2025-07-16 Size : 28kb User : Matgek
[VHDL-FPGA-Verilog] Floating-Point-Adder DL : 0: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Date : 2025-07-16 Size : 151kb User : 凌音
[VHDL-FPGA-Verilog] cordic-verilog DL : 0: 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
Date : 2025-07-16 Size : 1kb User : 朱子翰
[VHDL-FPGA-Verilog] PipeLine.tar DL : 0: Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
Date : 2025-07-16 Size : 2.79mb User : czl
[VHDL-FPGA-Verilog] pipelined-mips-cpu DL : 1: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Date : 2025-07-16 Size : 167kb User : jack chen
[VHDL-FPGA-Verilog] cpu DL : 0: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Date : 2025-07-16 Size : 2kb User : dylan
[VHDL-FPGA-Verilog] CPU-Pipeline DL : 0: 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
Date : 2025-07-16 Size : 14kb User : Si Cheng

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